Continued innovations in semiconductor process technologies are enabling higher integration densities and device scaling. As the semiconductor industry moves towards the 7 nanometer (nm) technology node and beyond, planar and non-planar semiconductor device structures, such as field-effect transistors (FETs) (e.g., metal-oxide-semiconductor FETs (MOSFETs)), must be scaled to smaller dimensions to provide increased device width per footprint area. In this regard, nanosheet (or nanowire) FET devices are considered to be a viable option for continued scaling. In general, a nanosheet FET device comprises a device channel having a nanosheet stack comprising one or more nanosheet layers, with each nanosheet layer having a vertical thickness that is substantially less than the width of the nanosheet layer. A common gate structure may be formed above and below each nanosheet layer in a stacked configuration, thereby increasing the FET device width (or channel width). Accordingly, such nanosheet FET devices may increase the drive current for a given footprint area.